s390x: Emit instructions for bitwise FP ops #12232
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cranelift requires that bitwise operations work across all
data types, including floating point. The prior implementation
of bitwise operations, xor in this example, would cause a panic
with the message:
no rule matched for term aluop_xor
This patch adds lowerings for bitwise operations on floating
point registers using the vector instructions and the vector
register overlay property of the s390x register file.
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The lowerings here look reasonable but would you mind adding a runtest (or adding s390x to an existing runtest if one exists) as well, to verify?
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Yes. I'll make sure this is part of a runtest. |
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So I added a simple test to bitops: which causes pulley to panic: So do I need to fix something in pulley to get this working? |
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I believe that's because Pulley doesn't implement bitwise fp ops, so you'll want to add a new |
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Is pulley missing these bitops something that we should track in Issue #12197 ? |
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Looks like aarch64 has a problem with fp bitops as well. |
pulley and aarch64 omitted as they currently fail this test
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I removed aarch64 from the fp-bitops test. I'm thinking this should pass now. |
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Thanks! It's fine I think to leave Pulley out of that issue since it's a much more constrained backend than the others, but thanks for the consideration! |
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cranelift requires that bitwise operations work across all data types, including floating point. The prior implementation of bitwise operations, xor in this example, would cause a panic with the message:
no rule matched for term aluop_xor
This patch adds lowerings for bitwise operations on floating point registers using the vector instructions and the vector register overlay property of the s390x register file.
Partially addresses Issue #12197